The present invention relates to a semiconductor device and more specifically to the construction of a gate turn-off thyristor (hereinafter referred to as GTO thyristor).
A GTO thyristor of the PNPN four-layer construction with a control electrode is capable of controlling large quantities of electric power as compared with the transistors. There has in the past been proposed a GTO thyristor equipped with an emitter short-circuiting layer on the anode side to enhance the self-turn-off ability. A semiconductor switch of the type in which the emitter is short-circuited on the anode side has been taught, for example, in FIGS. 6 and 7 of U.S. Pat. No. 3,239,728.
It has, however, been desired to produce a GTO thyristor of the type in which the emitter on the anode side is short-circuited and in which the connection points between the control electrode and the lead wire connected to the control electrode is minimized to as great an extent as possible. The width of the control electrode is in the order of several hundreds of um. Therefore, the portions remote from the connection point exhibits increased electric resistance which causes the turn-off time to be lengthened. Furthermore, the increase in the electric resistance makes it difficult to emit the carriers accumulated in the GTO thyristor to the external circuit via a lead wire when the GTO thyristor is turned off; i.e., the increase in the electric resistance makes it difficult to extract the accumulated carriers. This presents a serious hindrance when it is attempted to make GTO thyristors of large capacities.